this is the core of the cpu im trying to build. the first chip on lower right is an 8 bit counter. chip above that is pc address register, then mem address register
the orange bus is the output of the counter to the rest of the system. the left column is pc reg io, mem addr io, mem data io, and a 4th io for a special ram for jump optimization. all the io chips do is act as transcievers, with a data bus passing through them to the purple bus on the bottom. for example, mem reg io take the address loaded in mem addr reg, and passes this value through unchanged to the left. however, they also have a bus going down thru them, and the controller chip will tell which io chip will take its incoming data and throw it into the input bus, eventually reaching the purple bus on the left of the counter.
almost all this works, except this:
the output of the mem address register is 255. lines 0-7 are active. this should pass through unchanged to the left, but here the output shows only 1 single line active. it should be reading 255, not 1.
the mem io chip design:
here the inputs are the right and top. left and bottom are outputs. the right inputs just pass their signals on to the left side...if the cyan signal on the right goes up, itll activate the AND gates and send the right edge input data down the vertical bus. funny thing is this part works. but the left edge outputs? wtf. theres no reason why they should not always read whats on the right edge. its just passing through..there nothing to mess their values.